Evolution of Fault and Noise Tolerant Digital Circuits

The field of digital electronics has since its start been in constant progression. Integrated circuits are becoming more and more dense as there is a demand for more speed and functionality. A fundamental requirement which is increasingly hard to satisfy with this development is that the system does not fail. Fault tolerance and managing noise are both major long term challenges of the digital design domain. The work herein attacks the challenges of fault tolerance and robustness to noise through the application of evolutionary algorithms. Such algorithms search through possible solutions by implementing concepts from Darwin’s theories on natural evolution. Circuit designs are evolved that make use of messy gates, logic gates with inherent discrepancies. A simulator has been developed that evaluates the circuits whilst exposing them to different amounts of component failures and noise in the environment. The results are analysed in order to investigate how the different amounts of faults and noise influence the ability of the circuits to operate correctly. In the analysis of the results, the effect faults and noise have on the evolutionary process is examined. The size and complexity of the evolved circuits is limited by known scalability issues of evolutionary algorithms. The algorithms search through a space of all possible circuits that can be represented. The challenge faced by the evolutionary algorithm when the size of the problem is scaled up is the sheer size of this search space. The vast majority of the search space consists of circuits that have no useful features, a situation that could potentially be improved using more clever representations. One potential solution to the scalability issue that employs indirect representations is artificial development, methods inspired by the development of biological organisms. The evolved circuits are investigated in an attempt to uncover whether they are suited for the application of artificial development. These investigations are carried out through the analysis of the complexity of evolved circuits.